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| Comparison table of TMP86CM25F/CS25F/PS25F/C925XB and TMP86CM25AF/FM25F TMP86CM25F/ TMP86CS25F ROM RAM I/O External Interrupt AD Converter Timer Counter Serial Interface LCD Key-on Wakeup Operating Voltage in MCU Mode Operating Temperature in MCU Mode Writing to Flash Memory Package CPU Wait (Note 1) P-QFP100-1420-0.65A N/A 32 K (Mask ROM) 60 K (Mask ROM) 2K 42 pin 5 pin 8-bit AD converter x 8 ch 18-bit timer x 1 ch 8-bit timer x 4 ch 8-bit SIO x 2 ch UART x 1 ch 60 seg x 16 com 4 ch 1.8 to 5.5 V at 4.2 MHz 2.7 to 5.5 V at 8 MHz 4.5 to 5.5 V at 16 MHz -40 to 85 - FBGA272 1.8 to 5.25 V at 4.2 MHz 2.7 to 5.25 V at 8 MHz 4.5 to 5.25 V at 16 MHz 0 to 60C TMP86PS25F 60 K (OTP) TMP86C925XB (Emulation chip) - - 42 pin (MCU part) TMP86FM25F 32 K (Flash) 2K 42 pin 5 pin Difference TMP86CM25AF 32 K (Mask ROM) 8-bit AD converter x 8 ch (Note 3) 18-bit timer x 1 ch 8-bit timer x 4 ch 8-bit SIO x 2 ch UART x 1 ch 60 seg x 16 com (Note 4) 4 ch 1.8 to 3.6 V at 4.2 MHz (External clock) 1.8 to 3.6 V at 8 MHz (Resonator) 2.7 to 3.6 V at 16 MHz -40 to 85C 2.7 to 3.6V at 16 MHz 25C 5C Available (Note 2) - P-QFP100-1420-0.65A Note 1: The CPU wait is a CPU halt function for stabilizing of power supply of Flash memory. The CPU wait period is as follows. In the CPU wait period except RESET, CPU is halted but peripheral functions are not halted. Therefore, if the interrupt occurs during the CPU wait period, the interrupt latch is set. In this case, if the IMF has been set to "1", the interrupt service routine is executed after CPU wait period. For details refer to 1.1 "Flash Memory" in TMP86FM25F data sheet. Condition After reset release Changing from STOP mode to NORMAL mode (at EEPCR Wait Time 2 /fc[s] 2 /fc[s] 2 /fs[s] 2 /fc[s] 2 /fs[s] 3 10 3 10 10 Halt/Operate CPU Halt Halt Halt Halt Halt Peripherals Halt Operate Operate Operate Operate Note 2: Though the TMP86CM25AF does not have a Flash memory, the CPU wait function is inserted in TMP86CM25A to keep the compatibility with Flash product (TMP86FM25F). Note 3: AD conversion time of TMP86CM25A/FM25 is different from that of TMP86CM25/CS25/PS25/C925. For details, refer to 2.12 "8-Bit AD Converter (ADC)". Note 4: The reference voltage of TMP86CM25A/FM25 is different from that of TMP86CM25/CS25/ PS25/C925. For details, refer to "Electrical Characteristics". 2004-03-01 Under development CMOS 8-Bit Microcontroller TMP86FM25 TMP86FM25F The TMP86FM25 is a Flash type MCU which includes 32 Kbytes Flash memory. It is a pin compatible with a mask ROM product "A" version of the TMP86CM25A. Writing the program to built-in Flash memory, the TMP86FM25 operates as the same way as the TMP86CM25A. The TMP86FM25 has a 2 Kbytes BOOT ROM (Masked ROM) for programming to Flash memory. Product No. TMP86FM25F Flash Memory 32 K x 8 bits BOOT ROM 2 K x 8 bits RAM 2.0 K x 8 bits Package P-QFP100-1420-0.65A P-QFP100-1420-0.65A TMP86FM25F 030619EBP1 * The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 86FM25-1 2004-03-01 Under development TMP86FM25 Pin Assignments (Top view) P-QFP100-1420-0.65A VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 Note1: The masked ROM product (TMP86CM25AF/CM25F/CS25F), the OTP product (TMP86PS25F) and the emulation chip (TMP86C925XB) don't have a BOOT function in P15 pin. Note2: Ports assigned as MUL6 to MUL0 can switch pin assignment by the multifunction register (MULSEL). For functions assigned to each pin, see the table below. Pin Name MUL0 MUL1 MUL2 MUL3 MUL4 MUL5 MUL6 DVO PDO3 , PWM3 ,TC3 PDO4 , PWM4 , PPG4 ,TC4 PDO6 , PWM6 , PPG6 ,TC6 INT1 INT2 INT3 ( STOP / INT5 ) P20 (AIN0) P60 (AIN1/ECIN) P61 (AIN2/ECNT) P62 (AIN3/INT0) P63 (AIN4/STOP2) P64 (AIN5/STOP3) P65 (AIN6/STOP4) P66 (AIN7/STOP5) P67 VAREF (SEG59/SCK0) P17 (SEG58/TXD/SO0) P16 (BOOT/SEG57/RXD/SI0) P15 (SEG56/MUL6) P14 (SEG55/MUL5) P13 (SEG54/MUL4) P12 (SEG53) P11 (SEG52) P10 (SEG51/MUL3) P33 (SEG50/MUL2) P32 (SEG49/MUL1) P31 (SEG48/MUL0) P30 RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 COM2 COM3 COM4 (MUL4/COM5) P34 (MUL5/COM6) P35 (MUL6/COM7) P36 (COM8) P70 (MUL0/COM9) P71 (MUL1/COM10) P72 (MUL2/COM11) P73 (MUL3/COM12) P74 (SI1/COM13) P75 (SO1/COM14) P76 (SCK1/COM15) P77 V4 V3 V2 V1 C1 C0 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 P50 (SEG40) P51 (SEG41) P52 (SEG42) P53 (SEG43) P54 (SEG44) P55 (SEG45) P56 (SEG46) P57 (SEG47) Function Pin Assignment P30 or P71 P31 or P72 P32 or P73 P33 or P74 P12 or P34 P13 or P35 P14 or P36 86FM25-2 2004-03-01 Under development Block Diagram I/O port (Segment output) Common outputs COM4 to COM0 Segment outputs SEG39 to SEG0 P57 (SEG47) to P50 (SEG40) P17 (SEG59) to P10 (SEG52) TMP86FM25 Power supply VDD VSS LCD driver circuit C0 C1 V1 V2 V3 V4 P5 P1 LCD power supply LCD voltage booster circuit TLCS-870/C CPU System control circuit Standby control circuit (Key-on wakeup) Timing generator Time base timer Watchdog timer Address/data bus Reset input test pin RESET TEST Data memory (RAM) Program memory (Flash) Interrupt Controller Resonator connecting pins XIN XOUT High frequency Clock generator Low frequency 18-bit timer/counter TC1 8-bit timer/counter SIO UART TC3 TC4 TC5 TC6 SIO1 SIO0 Address/data bus P2 P6 P3 P3 P7 8-bit AD converter P22 to P20 VAREF P67 (AIN7) P36 (COM7) P33 (SEG51) to to to P60 (AIN0) P34 (COM5) P30 (SEG48) I/O ports P77 (COM15) to P70 (COM8) I/O ports Analog reference pins 86FM25-3 2004-03-01 Under development Pin Funtions The TMP86FM25 has MCU mode and serial PROM mode. (1) MCU mode TMP86FM25 In the MCU mode, the TMP86FM25 is a pin compatible with the TMP86CM25A (Make sure to fix the TEST pin to low level). (2) Serial PROM mode In the Serial PROM mode, programming to Flash memory is available by executing BOOT ROM. In the serial PROM mode, TXD (P16) and RXD (P15) pins are used as a serial interface pin. Therefore, if the programming is executed on-board after mounting, these pins should be released from the other devices for communication in serial PROM mode. 86FM25-4 2004-03-01 Under development 1.1 FLASH Memory Outline TMP86FM25 1.1.1 The TMP86FM25 incorporates 32768 bytes of FLASH memory (Address 8000H to FFFFH). The writing to FLASH is controlled by FLASH control register (EEPCR), FLASH status register (EEPSR). To write data to the FLASH, execute the Serial PROM mode. For details about the Serial PROM mode, refer to "2.1 Serial PROM Mode". The FLASH memory of the TMP86FM25 features: * * The FLASH memory is constructed of 512 pages FLASH memory and one page size is 64 bytes (512 pages x 64 bytes = 32768 bytes). The TMP86FM25 incorporates a 64-byte temporary data buffer. The data written to FLASH memory is temporarily stored in this data buffer. After 64 bytes data have been written to the temporary data buffer, the writing to FLASH memory automatically starts by page writing (The 64 bytes data are written to specified page of FLASH simultaneously). At the same time, page-by-page erasing occurs automatically. So, it is unnecessary to erase individual pages in advance. The FLASH control circuit incorporates an oscillator dedicated to the FLASH. So FLASH writing time is independent of the system clock frequency (fc). In addition, because an FLASH control circuit controls writing time for each FLASH memory cell, the writing time varies in each page (Typically 4 ms per page). Controlling the power for the FLASH control circuit (Regulator and voltage step-up circuit) achieves low power consumption if the FLASH is not in use (Example: When the program is executed in RAM area). * * 1.1.2 Conditions for Accessing the FLASH Areas The conditions for accessing the FLASH areas vary depending on each operation mode. The following tables shows FLASH are access conditions. Table 1.1.1 FLASH Area Access Conditions Area FLASH memory 8000H to FFFFH Operation Mode MCU Mode (Note 1) Read/Fetch only Serial PROM Mode (Note 2) Write/Read/Fetch supported Note 1: "MCU Mode" shows NORMAL1/2 and SLOW1/2 modes. Note 2: "Serial PROM Mode" shows the FLASH controlling mode. For details, refer to 2.1 "Serial PROM Mode". Note 3: "Fetch" means reading operation of FLASH data as an instruction by CPU. 86FM25-5 2004-03-01 Under development 1.1.3 Differences among Product Series TMP86FM25 The specifications of the FLASH product (TMP86FM25) are different from TMP86CM25A (Masked ROM "A" version), TMP86C925XB (Emulation chip), TMP86CM25F/CS25F (Masked ROM) and TMP86PS25 (OTP) as listed below. See 1.2.2 "Control" for explanations about the control registers. Masked ROM "A" Version (TMP86CM25AF) Neither the EEPMD nor EEPRS itself does not function. (Writing to an area that corresponds to the FLASH area causes nothing.) The Current Products TMP86C925XB (Emulation chip) TMP86CM25F/CS25F (Mask ROM) TMP86PS25F (OTP) The FLASH function is not executed because the emulation chip and the MASK (except "A" version)/OTP products don't have EEPCR and EEPSR registers. Therefore, the software including the FLASH register can not be emulated by the emulation chip. If the software including the FLASH register is executed in the MASK (except "A" version)/OTP or the emulation chip, the software process differs from the FLASH product. FLASH Product (TMP86FM25) It is possible to rewrite the EEPCR register only when the program execution area in use is RAM/BOOT-ROM. Typically 4 ms (Independent of the system clock) If EEPSR Rewriting the EEPCR register FLASH write time Executing a read instruction/fetch to the 8000H to FFFFH area when EEPSR Always masked ROM data is read. Executing a write instruction to the 8000H to FFFFH area when EEPCR MCU mode Serial PROM mode The EEPSR CPU wait for Flash (Wait period for stabilizing of the power supply of Flash control circuit) The wait period is inserted in the releasing from Reset, STOP mode (EEPCR The wait period is not inserted. Even if the FLASH register is not used for software, the Reset and STOP process differs from the FLASH product. The current products don't have BOOT-ROM. Therefore, the serial PROM mode can not be emulated in the current products. BOOT-ROM 2 Kbytes are included in the 3800H to 3FFFH area. Operating voltage (VDD) 1.8 to 3.6 V (1 MHz to 4.2 MHz: External clock) 1.8 to 3.6 V (1 MHz to 8 MHz: Resonator) 2.7 to 3.6 V (1 MHz to 16 MHz) 1.8 to 5.5 V (1 MHz to 4.2 MHz) 2.7 to 5.5 V (1 MHz to 8 MHz) 4.5 to 5.5 V (1 MHz to 16 MHz) The maximum voltage of the TMP86C925XB is 5.25 V. 86FM25-6 2004-03-01 Under development 1.1.4 FLASH Memory Configuration TMP86FM25 64 consecutive bytes in the FLASH area are treated as one group, which is defined as a page. The TMP86FM25 incorporates a one-page temporary data buffer. Writing data to FLASH is temporarily stored in this 64-byte data buffer. After 64 bytes data have been written to the temporary data buffer, these data are written to specified page of FLASH at a time. However, data can be read from any address byte by byte. 1.1.4.1 Page Configuration The FLASH area has a page configuration of 64 bytes/page as shown below. The total number of bytes in it is 512 pages x 64 bytes (= 32768 bytes). The writeable area is 8000H to FFFFH in Serial PROM mode. Note: The FLASH area (8000H to FFFFH) can be written only in the Serial PROM mode. For details of the Serial PROM mode, refer to 2.1 "Serial PROM Mode". 2 3 4 5 6 7 8 9 A B C D E F Address 8000H 8010H 8020H 8030H 8040H 8050H 8060H 8070H 8080H 8090H 80A0H 80B0H 80C0H 80D0H 80E0H 80F0H 0 1 Page 0 Page 1 Page 2 Page 3 Page 511 FFE0H FFF0H Figure 1.1.1 Page Configuration 86FM25-7 2004-03-01 Under development 1.2 FLASH Memory Control Circuit Configuration TMP86FM25 1.2.1 Address input 16 Temporary data buffer 512 (64 bytes) with write Overflow data counter D Q Q Regulator VIN 8 Count up Data input Write time Overflow counter EN FLASH Memory Clear CP CPR End of write Serial PROM mode FLASH area chip select signal CPU WAIT signal Address bus Data bus RAM/BOOT-ROM fetch signal WR signal SYSCR1 Overflow SYSCR2 Decoder MNPWDW ATPWDW 4 EEPMD EEPRS D Request to generate an interrupt vector Q BFBUSY EWUPEN CP R WINT EEPSR RD signal EEPCR EEPSR Figure 1.2.1 FLASH Memory Control 86FM25-8 2004-03-01 Under development 1.2.2 Control TMP86FM25 The FLASH memory is controlled by FLASH control register (EEPCR) and FLASH status register (EEPSR). These registers are assigned to DBR. Address 0F90H 91 92 93 94 95 96 97 98 99 9A 9B 9C 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA BF C0 C1 DF E0 E1 E2 FF Read SIO0BR0 (SIO0 buffer 0) SIO0BR1 (SIO0 buffer 1) SIO0BR2 (SIO0 buffer 2) SIO0BR3 (SIO0 buffer 3) SIO0BR4 (SIO0 buffer 4) SIO0BR5 (SIO0 buffer 5) SIO0BR6 (SIO0 buffer 6) SIO0BR7 (SIO0 buffer 7) - SIO0SR (SIO0 status register) - RDBUF (UART received data buffer) Reserved SIO1BR0 (SIO1 buffer 0) SIO1BR1 (SIO1 buffer 1) SIO1BR2 (SIO1 buffer 2) SIO1BR3 (SIO1 buffer 3) SIO1BR4 (SIO1 buffer 4) SIO1BR5 (SIO1 buffer 5) SIO1BR6 (SIO1 buffer 6) SIO1BR7 (SIO1 buffer 7) - SIO1SR (SIO1 status register) Write SIO0CR1 (SIO0 control register 1) SIO0CR2 (SIO0 control register 2) STOPCR (Key-on wakeup control register) TDBUF (UART transmit data buffer) Reserved SIO1CR1 (SIO1 control register 1) SIO1CR2 (SIO1 control register 2) Reserved Reserved MULSEL (Multiplexed function select register) Reserved Reserved EEPCR (Flash memory control) EEPSR(Flash memory status) Reserved Reserved - Note 1: Do not access reserved areas by the program. Note 2: -: Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Figure 1.2.1 The Data Buffer Register (DBR) for TMP86FM25 86FM25-9 2004-03-01 Under development TMP86FM25 FLASH Control Register 7 6 5 EEPCR EEPMD (0FE0H) 4 3 2 EEPRS 1 0 (Initial value: 1100 *011) Program Execution Area RAM/ BOOT FLASH ATPWDW MNPWDW EEPMD FLASH write enable control (Write protect). 1100: FLASH write disable. 0011: FLASH write enable. Other values: Reserved. 0: - 1: FLASH writing is forced to stop. (The write data counter is initialized.) * After writing "1" to EEPRS, it is automatically cleared to "0". 0: Automatic power shut down is executed in IDLE0/1/2 and SLEEP0/1/2 modes. 1: Automatic power shut down is not executed in IDLE0/1/2 and SLEEP0/1/2 modes. (The power is always supplied in these modes.) 0: The power for the FLASH control circuit is turned off. 1: The power for the FLASH control circuit is turned on. EEPRS FLASH write forcible stop. Read only ATPWDW Automatic power control for the FLASH control circuit in the IDLE0/1/2, SLEEP0/1/2 modes. (This bit is available only when MNPWDW is set to "1".) Software-based power control for the FLASH control circuit. R/W R/W MNPWDW Read only Note 1: The EEPMD, EEPRS, and MNPWDW can be rewritten only when a program fetch is taking place in the RAM or BOOT-ROM area. If an attempt is made to rewrite the EEPCR register when a program is being executed in the FLASH area, the EEPMD, EEPRS, and MNPWDW keep holding the previous data; they are not rewritten. Note 2: To write to the FLASH, set the EEPMD with "0011B" in advance when a program fetch is taking place in the RAM area. Note 3: Note 4: To forcibly stop writing of FLASH, set the EEPRS to "1" when a program fetch is taking place in the RAM area. The ATPWDW functions only if the MNPWDW is "1". If the MNPWDW is "0", the power for the FLASH control circuit is kept turned off regardless of the setting of the ATPWDW. Note 5: When a STOP mode is executed, the power for the FLASH control circuit is turned off regardless of the setting of the ATPWDW. If the MNPWDW is "0", entering/exiting the STOP mode allows the power for the FLASH control circuit to be kept turned off. Note 6: Note 7: Executing a read instruction to the EEPCR register results in bit3 being read as undefined. Bit2 is always read as "0". The following attention is necessary when the MNPWDW is set or cleared. When the MNPWDW is changed from "1" to "0" Clear the interrupt master enable flag (IMF) to "0" in advance to disable an interrupt. After that, do not set IMF to "1" during EEPSR When the MNPWDW is changed from "0" to "1" Note 8: In MCU mode, the EEPMD and EEPRS should be set to "1100B" and "0". Figure 1.2.2 FLASH Control Register 86FM25-10 2004-03-01 Under development TMP86FM25 FLASH Status Register 7 EEPSR (0FE1H) 6 5 4 3 2 WINT 1 0 (Initial value: **** *010) EWUPEN BFBUSY WINT Interrupt detection during a write to the FLASH Control circuit status 0: Not detected 1: Detected (Interrupt occurred) * WINT is automatically cleared to "0" when read instruction is executed to EEPSR. Operating (Power on) Writing 1 1 Halt (Power off) or warm-up Disable 0 1 Read only EWUPEN FLASH control Temporary data circuit status monitor FLASH status buffer empty 1 FLASH write busy flag 0 BFBUSY Note 1: If a nonmaskable interrupt occurs during a write to the FLASH, the WINT is set to "1" and the writing is discontinued, and then warm-up period (CPU wait) for the control circuit of Flash memory is executed. (The write data counter is initialized.) If WINT = "1" is detected in the nonmaskable interrupt service routine, a write is not completed successfully. So, it is necessary to try a write again. The content of the page to which a write is taking place may be changed to an unexpected value depending on the timing when the WINT becomes "1". Note 2: Even if a nonmaskable interrupt occurs during an FLASH warm-up , the CPU stays at a halt until the warm-up is finished. Note 3: Note 4: The WINT is automatically cleared to "0" when a read instruction is executed to the EEPSR register. When MNPWDW is changed from "0" to "1", EWUPEN becomes "1" after taking 210/fc [s] (if SYSCK = "0") or 23/fs [s] (if SYSCK = "1"). Before accessing the FLASH, make sure that the EWUPEN is "1" in the RAM area. Note 5: If the BFBUSY is "1", executing a read instruction or fetch to the FLASH area causes FFH to be read. Fetching FFH results in a software interrupt occurring. Note 6: In the TMP86CM25A, if the EWUPEN is "1", writing to the masked ROM area that corresponds to the FLASH area does not set the BFBUSY of the TMP86CM25A to "1". Figure 1.2.3 FLASH Status Register 86FM25-11 2004-03-01 Under development 1.2.3 FLASH Write Enable Control (EEPCR TMP86FM25 In the FLASH product, the control register can be used to disable a write to the FLASH (Write protect) in order to prevent a write to the FLASH from occurring by mistake because of a program error or microcontroller malfunction. To enable a write to the FLASH, set the EEPCR 86FM25-12 2004-03-01 Under development 1.2.4 FLASH Write Forcible Stop (EEPCR TMP86FM25 To forcibly stop a write to the FLASH, set the EEPCR Example: Reads the Flash memory data immediately after setting EEPCR Note 6: This function can be used in serial PROM mode. In this mode, the EEPCR 86FM25-13 2004-03-01 Under development TMP86FM25 Buffer 0 Buffer 1 Buffer 2 Buffer 63 EEPCR ? ? Data 0 Data 0' Data 1' Data 1 ? ? Write to the EPCR Data 2' 0 1 2 0 0 1 2 3 4 5 210/fc or 23/fs [s] Overflow 0 Normal operation Warm-up in progress (CPU wait) 0 Normal operation Figure 1.2.4 Write Data Counter Initialization and Write Forcible Stop 86FM25-14 2004-03-01 Under development 1.2.5 Power Control for the FLASH Control Circuit TMP86FM25 For the FLASH product, it is possible to turn off the power for FLASH control circuit (such as a regulator) to suppress power consumption if the FLASH area is not accessed. For the TMP86CM25A, the register setting and the CPU wait functions behave in the same manner as for the FLASH product to maintain compatibility; however, power consumption is not suppressed. The EEPCR 10 SLOW1/2 3 STOP Mode (when EEPCR To Return to a NORMAL Mode STOP warm-up time + 210/fc [s] To Return to a SLOW Mode STOP warm-up time + 23/fs [s] IDLE0/1/2 Mode SLEEP0/1/2 Mode 2 /fc [s] (64 s at 16 MHz) 2 /fs [s] (244 s at 32.768 kHz) 1.2.5.1 Software-based Power Control for the FLASH Control Circuit (EEPCR 9. Keep program polling until the EEPSR 86FM25-15 2004-03-01 Under development TMP86FM25 If the EEPCR Specify MNPWDW = 0 EEPCR Figure 1.2.5 Software-based Power Control for the FLASH Control Circuit (EEPCR 86FM25-16 2004-03-01 Under development TMP86FM25 Example: Performing software-based power control for the FLASH control circuit sRAMAREA: DI ; Disable an interrupt (IMF "0"). ; Clear the binary counter if the watchdog timer LD (WDTCR2),4Eh ; is in use. CLR sLOOP1: SET TEST JRS JP (EEPCR).0 (EEPCR).0 (EEPSR).1 T,sLOOP1 MAIN ; ; ; ; ; Clear the EEPCR 86FM25-17 2004-03-01 Under development 1.2.5.2 TMP86FM25 Automatic Power Control for the FLASH Control Circuit (EEPCR EEPCR IDLE or SLEEP mode 210/fc or 23/fs [s] 0 Warm-up in progress CPU WAIT Normal operation FLASH control circuit status Operation mode Program execution area NORMAL or SLOW mode NORMAL or SLOW mode FLASH area or RAM area Figure 1.2.6 Automatic Power Control for the FLASH Control Circuit (EEPCR 86FM25-18 2004-03-01 Under development 1.2.6 Accessing to the FLASH Memory TMP86FM25 During the writing to the FLASH area, neither a read nor fetch can be performed for the 8000H to FFFFH area. Therefore, to write the FLASH area, the program should be executed in the BOOTROM or RAM area. Basically, to write the FLASH area, the program can be executed in BOOTROM area by using the FLASH writing mode of the Serial PROM mode, but it can be also executed any user program in RAM area by using the RAM loader mode of the Serial PROM mode. Explanation here is made of only the method of FLASH programming in RAM area. For detail about each operation mode of the Serial PROM mode, refer to 2.1 "Serial PROM Mode". Although the writing to FLASH is executed on page-by-page, the reading from FLASH is executed on byte-by-byte. If a nonmaskable interrupt occurs during a write to the FLASH (EEPSR 86FM25-19 2004-03-01 Under development 1.2.6.1 FLASH Writing Program in the RAM Area TMP86FM25 To develop the program in RAM, the write control program should be loaded from external device by using RAM loader mode in Serial PROM mode. Given below is an example of writing the control program in the RAM area. (1) Example of writing program in the RAM area 1. Monitor the EEPSR 2. 3. 4. 5. 6. Note: 86FM25-20 2004-03-01 Under development (2) Method of specifying an address for a write to the FLASH TMP86FM25 The FLASH page to be written is specified by the 10 high-order bits of the address of the first byte data. The first byte data is stored at the first address of the temporary data buffer. If the data to be written is, for example, 8040H, page 1 is selected, and the data is stored at the first address of the temporary data buffer. Even if the 6 low-order bits of the specified address is not 000000B, the first byte data is always stored at the first address of the data buffer. Any address can be specified as the second and subsequent address within FLASH area (8000H to FFFFH). The write data bytes are stored in the temporary data buffer in the sequence they are written, regardless of what address is specified. Usually, the address that is the same as the first byte is specified for the second and subsequent address. A 16-bit transfer instruction (LDW) can also be used for writing to the temporary data buffer. Example: Data bytes 00H to 3FH are written to page 1. (Figure 1.2.9 shows the example of data buffer and pages.) DI LD LD LD LD sLOOP1: LD (IX),C ; Store data to the temporary data buffer. (A write page is selected when the first byte is written.) C = C + 1. Jump to sLOOP1 if C is not 40H. ; C,00H HL,EEPCR IX,8040H (HL),3BH ; ; ; Disable an interrupt (IMF "0"). Specify the EEPCR register address. Specify a write address. Specify the EEPCR. INC CMP JR sLOOP2: TEST JRS LD C C,40H NZ,sLOOP1 (EEPSR).0 F,sLOOP2 (HL),0CBH ; ; ; ; Jump to sLOOP2 if EEPSR Note: If the BFBUSY is "1", executing a read instruction or fetch to the FLASH area causes "FFH" to be read. Fetching "FFH" results in a software interrupt occurring. 86FM25-21 2004-03-01 Under development TMP86FM25 0 00H 10H 20H 30H Address 8030H 8040H 8050H 8060H 8070H 00H 10H 20H 30H 0 1 01H 11H 21H 31H 1 01H 11H 21H 31H 2 02H 12H 22H 32H 2 02H 12H 22H 32H 3 03H 13H 23H 33H 3 03H 13H 23H 33H 4 04H 14H 24H 34H 4 04H 14H 24H 34H 5 05H 15H 25H 35H 5 05H 15H 25H 35H 6 06H 16H 26H 36H 6 06H 16H 26H 36H 7 07H 8 08H 9 09H 19H 29H 39H 9 09H 19H 29H 39H A 0AH 1AH 2AH 3AH A 0AH 1AH 2AH 3AH B 0BH 1BH 2BH 3BH B 0BH 1BH 2BH 3BH C 0CH 1CH 2CH 3CH C 0CH 1CH 2CH 3CH D 0DH 1DH 2DH 3DH D 0DH 1DH 2DH 3DH E 0EH 1EH 2EH 3EH E 0EH 1EH 2EH 3EH F 0FH 1FH 2FH 3FH F 0FH 1FH 2FH 3FH Temporary data buffer 37H 7 07H 38H 8 08H Page 1 37H 38H Figure 1.2.7 Data Buffer and Write Page (Example) 86FM25-22 2004-03-01 Under development TMP86FM25 Buffer 0 Buffer 1 Buffer 2 Buffer 63 FLASH cell Write instruction to the FLASH area Write data counter EEPSR ? ? Data 0 Data 1 64 bytes are written at a time. Data 2 Data 63 Data before writing Erasing Writing Data after writing Overflow 0 1 2 3 63 0 Write completed Write time (Typically 4 ms) ? ? Figure 1.2.8 Write to the FLASH Area 86FM25-23 2004-03-01 Under development 2.1 Serial PROM Mode Outline TMP86FM25 2.1.1 The TMP86FM25 has a 2-Kbyte BOOT-ROM for programming to FLASH memory. This BOOT-ROM is a mask ROM that contains a program to write the FLASH memory on-board. The BOOT-ROM is available in a serial PROM mode and it is controlled by P11 pin, BOOT (P15) pin, TEST pin and RESET pin, and is communicated via TXD (P16) and RXD (P15) pins. There are four operation modes in a serial PROM mode: FLASH writing mode, RAM loader mode, FLASH memory SUM output mode and Product discrimination code output mode. Operating area of serial PROM mode differs from that of MCU mode. The operating area of serial PROM mode shows in Table 2.1.1. Table 2.1.1 Operating Area of Serial PROM Mode Parameter Operating voltage High frequency (Note) Temperature Min 2.7 2 25 5 Max 3.6 16 Unit V MHz C Note: Even though included in above operating area, part of frequency can not be supported in serial PROM mode. For details, refer to Table 2.1.6. 2.1.2 Memory Mapping The BOOT-ROM is mapped in address 3800H to 3FFFH. The Figure 2.1.1 shows a memory mapping. 0000H SFR RAM 083FH 0F80H DBR 0FFFH 3800H BOOT ROM 3FFFH 8000H FLASH 32768 bytes FFFFH 2048 bytes 128 bytes 003FH 0040H 64 bytes 2048 bytes Figure 2.1.1 Memory Address Maps 86FM25-24 2004-03-01 Under development 2.1.3 Serial PROM Mode Setting Serial PROM Mode Control Pins TMP86FM25 2.1.3.1 To execute on-board programming, start the TMP86FM25 in serial PROM mode. Setting of a serial PROM mode is shown in Table 2.1.2. Table 2.1.2 Serial PROM Mode Setting Pin BOOT/RXD pin (P15) P11 pin Setting High Low RESET , TESTpin 2.1.3.2 Pin Function In the serial PROM mode, TXD (P16) and RXD (P15) pins are used as a serial interface pin. Table 2.1.3 Pin Function in the Serial PROM Mode Pin Name (Serial PROM mode) TXD RXD/BOOT RESET Input/ Output Output Input Input Input Input Power supply Serial data output Function Pin Name (MCU mode) P16 (Note 1) P15 RESET Serial PROM mode control/Serial data input Serial PROM mode control Serial PROM mode control Serial PROM mode control (Fix to "L" level) 2.7 V to 3.6 V 0V Open or equal with VDD TEST P11 VDD VSS VAREF P10, P12 to P14, P17 P20 to P22 P30 to P36 P50 to P57 P60 to P67 P70 to P77 SEG39 to SEG0 COM4 to COM0 C0, C1, V4 to V1 XIN XOUT TEST P11 I/O Placed in High-Z state during serial PROM mode. Output Open LCD voltage booster pin Input Output Resonator connecting pins for high-frequency clock. For inputting external clock, XIN is used and XOUT is opened. (Note 2) Note 1: When the device is used as on-board writing and other parts are already mounted in place, be careful no to affect these communication control pins. Note 2: Operating area of high frequency in serial PROM mode is from 2 MHz to 16 MHz. 86FM25-25 2004-03-01 Under development TMP86FM25 To set a serial PROM mode, connect device pins as shown in Figure 2.1.2. TMP86FM25 VDD VAREF VDD (2.7 V~3.6 V) P11 GND VDD XIN TXD(P16) BOOT / RXD(P15) XOUT GND GND RESET Serial PROM mode MCU mode External control TEST Figure 2.1.2 Serial PROM Mode Port Setting 86FM25-26 2004-03-01 Under development 2.1.3.3 Activating Serial PROM Mode TMP86FM25 The following is a procedure of setting of serial PROM mode. Figure 2.1.3 shows a serial PROM mode timing. (1) Turn on the power to the VDD pin. (2) Set the P11 pin, TEST pin and RESET pin to low level. (3) Set the BOOT/RXD pin (P15) to high level. (4) Wait until the power supply and clock sufficiently stabilize. (5) Set the TEST pin from low level to high level. (6) Release the RESET . (Set to high level) (7) Input a matching data (5AH) to RXD pin after waiting for setup sequence. VDD P11(Input) Tsint (Initialization time for TEST pin) For executing RESET again Tssup TEST(Input) RESET (Input) Indeterminate VIH Tssup (Setup time for TEST pin) VIL VIH Rstf (Rising time of RESET pin) Rstf Reset mode Warm-up Serial PROM mode PROGRAM RXD (Input) Reset mode Warm-up Serial PROM mode Setup time for Serial PROM mode (Rxsup) Matching data (5Ah) input Setup time for Serial PROM mode (Rxsup) Matching data (5Ah) input Figure 2.1.3 Serial PROM Mode Timing Table 2.1.4 Serial PROM Mode Timing characteristics Parameter Setup time for TEST pin Initialization time for TEST pin Time from reset release until acceptance of start bit of RXD pin Rstf > 512 / fc [s] Rstf < 512 / fc [s] Tsint RXsup Symbol Tssup The Number of Clock (fc) 110000 Required Minimum Time at fc = 2 MHz 0 at fc = 16 MHz 1 ms *Note1 1ms 55 ms 6.9 ms Note 1: If Rstf is shorter than 512 / fc[s] due to using CMOS-type reset IC or Logic IC, the TEST pin can input the same pulse as the RESET pin input. (TEST pin can be directly connected to the RESET pin.) However, drive the pins carefully not to affect the pin's input level, as the TEST pin and the RESET pin have pull-down resistor and pull-up resistor built-in. Note 2: fc; High-frequency clock 86FM25-27 2004-03-01 Under development 2.1.3.4 Examples of On-board writing Figure 2.1.4 shows examples of On-board writing. TMP86FM25 TMP86FM25 VDD VDD (2.7 V~3.6 V) VAREF (SEG53) P11 LCD panel Reset control (Note5) Level Converter Logic IC RESET GND (Note2) VDD (Note1) (P16/SEG58/SO0) TXD (BOOT/P15/SEG57/SI0) RXD To PC VDD Serial PROM mode MCU mode (Note4) GND (Note3) RC power on reset circuit External control board TEST GND Application board Figure 2.1.4 Examples of Onboard writing Note 1: If capacity for LCD panel and other devices on the application board affect UART communication in Serial PROM mode, disconnect these pins by using a jumper or a switch. Note 2: Set the P11 pin to GND. There are two ways. Set P11 pin to GND on the external board, or set it to GND by setting a jumper on the application board. Note 3: If input signal has analog delay due to the use of such circuit as RC power on reset circuit, connect both TEST pin and RESET pin to logic ICs (Schmitt input IC such as TC74HC14). In this case, control the pin capacity to require the condition Rstf<512/fc[s]. Note4: In MCU mode, the TEST pin can be disconnected as it has a pull-down resistor built-in. However, we recommend connecting it to GND level to avoid noise influence. Note5: If the RESET control circuit on the application board affects the Serial PROM mode to start, disconnect it by using a jumper, etc. 86FM25-28 2004-03-01 Under development 2.1.4 Interface Specifications for UART TMP86FM25 The following shows the UART communication format used in serial PROM mode. Before on-board programming can be executed, the communication format on the external controller side must also be set up in the same way as for this product. Note that although the default baud rate is 9600 bps, it can be changed to other values as shown in Table 2.1.5. The Table 2.1.6 shows an operating frequency and baud rate in serial PROM mode. Except frequency which is not described in Table 2.1.6 can not use in serial PROM mode. Baud rate (Default): 9600 bps Data length: 8 bits Parity addition: None Stop bit length: 1 bit Table 2.1.5 Baud Rate Modification Data Baud rate modification data Baud rate (bps) 04H 76800 05H 62500 06H 57600 07H 38400 0AH 31250 18H 19200 28H 9600 86FM25-29 2004-03-01 Under development Table 2.1.6 Operating Frequency and Baud Rate in Serial PROM Mode Reference Baud Rate (bps) (Note 3) Baud Rate Modification Data Reference Frequency (MHz) 1 2 2 4 4.19 3 4.9152 5 4 5 6 7 6 6.144 7.3728 8 9.8304 10 12 8 12.288 12.5 9 10 14.7456 16 TMP86FM25 76800 04H Baud Rate (bps) - - - - - - - - - 76800 78125 - - - - 62500 05H 57600 06H 38400 07H 31250 0AH 19200 18H 9600 28H Area (MHz) 1.91~2.10 3.82~4.19 3.82~4.19 4.70~5.16 4.70~5.16 5.87~6.45 5.87~6.45 7.05~7.74 7.64~8.39 9.40~10.32 9.40~10.32 11.75~12.90 11.75~12.90 11.75~12.90 14.10~15.48 (%) - - - - - - - - - 0.00 +1.73 - - - - +0.16 (bps) - - - - - - - (%) - - - - - - - - (bps) - - - - - - - 57600 57692 59077 60096 57600 - (%) - - - - - - - 0.00 - - - +0.16 +2.56 +4.33 0.00 - (bps) - - - 38400 39063 38462 38400 39063 38400 38462 (%) - - - 0.00 +1.73 - - - +0.16 0.00 +1.73 - - - 0.00 +0.16 (bps) - 31250 32734 - - - - - 31250 - - 31250 32000 30048 - 31250 (%) - 0.00 +4.75 - - - - - 0.00 - - 0.00 +2.40 -3.85 - 0.00 (bps) - 19231 20144 19200 19531 - - 19200 19231 19200 19531 18750 19200 19531 19200 19231 (%) - +0.16 +4.92 0.00 +1.73 - - 0.00 +0.16 0.00 +1.73 -2.34 0.00 +1.73 0.00 +0.16 (bps) 9615 9615 10072 9600 9766 9375 9600 9600 9615 9600 9766 9375 9600 9766 9600 9615 (%) +0.16 +0.16 +4.92 0.00 +1.73 -2.34 0.00 0.00 +0.16 0.00 +1.73 -2.34 0.00 +1.73 0.00 +0.16 62500 - - - - 60096 - 62500 0.00 - - - - -3.85 - 0.00 15.27~16.77 76923 Note 1: "Reference Frequency" and "Area" show the high-frequency area supported in serial PROM mode. Except the above frequency can not be supported in serial PROM mode even though the high frequency is included in area from 2 MHz to 16 MHz. Note 2: The total error of frequency must be kept within +/-3% so that the auto-detection of frequency is executed correctly. Note 3: An external controller should transmit a matching data repeatedly till the TMP86FM25 transmit an echo back data. Above number indicates a transmission number of times of matching data till transmission of echo back data. 2.1.5 Command There are five commands in serial PROM mode. After reset release, the TMP86FM25 waits a matching data (5AH). Table 2.1.7 Command in Serial PROM Mode Command Data 5AH 30H 60H 90H C0H Operation Mode Setup FLASH memory writing RAM loader FLASH memory SUM output Product discrimination code output Remarks Matching data. Always start with this command after reset release. Writing to area from 8000H to FFFFH is enable. Writing to area from 0050H to 082FH is enable. The checksum of entire FLASH area (from 8000H to FFFFH) is output in order of the upper byte and the lower byte. Product discrimination code, that is expressed by 13 bytes data, is output. 86FM25-30 2004-03-01 Under development 2.1.6 Operation Mode TMP86FM25 There are four operating modes in serial PROM mode: FLASH memory writing mode, RAM loader mode, FLASH memory SUM output mode and Product discrimination code output mode. For details about these modes, refer to (1) FLASH memory writing mode through (4) Product discrimination code output mode. (1) FLASH memory writing mode The data are written to the specified FLASH memory addresses. The controller should send the write data in the Intel Hex format (Binary). For details of writing data format, refer to 2.1.7 "FLASH Memory Writing Data Format". If no errors are encountered till the end record, the SUM of 32 Kbytes of FLASH memory is calculated and the result is returned to the controller. To execute the FLASH memory writing mode, the TMP86FM25 checks the passwords except a blank product. If the passwords did not match, the program is not executed. (2) RAM loader mode The RAM loader transfers the data into the internal RAM that has been sent from the controller in Intel Hex format. When the transfer has terminated normally, the RAM loader calculates the SUM and sends the result to the controller before it starts executing the user program. After sending of SUM, the program jumps to the start address of RAM in which the first transferred data has been written. This RAM loader function provides the user's own way to control on-board programming. To execute the RAM loader mode, the TMP86FM25 checks the passwords except a blank product. If the passwords did not match, the program is not executed. (3) FLASH memory SUM output mode The SUM of 32 Kbytes of FLASH memory is calculated and the result is returned to the controller. The BOOT ROM does not support the reading function of the FLASH memory. Instead, it has this SUM command to use. By reading the SUM, it is possible to manage Revisions of application programs. (4) Product discrimination code output mode The product discrimination code is output as a 13-byte data, that includes the start address and the end address of ROM (In case of TMP86FM25, the start address is 8000H and the end address is FFFFH). Therefore, the controller can recognize the device information by using this function. 86FM25-31 2004-03-01 Under development 2.1.6.1 FLASH Writing Mode (Operation command: 30H) Table 2.1.8 shows FLASH memory writing mode process. Table 2.1.8 FLASH Writing Mode Process Number of Bytes Transferred BOOT ROM 1st byte 2nd byte 3rd byte 4th byte Transfer Data from External Controller to TMP86FM25 Matching data (5AH) - Baud rate modification data (See Table 2.1.5) - Baud Rate 9600 bps 9600 bps 9600 bps 9600 bps TMP86FM25 Transfer Data from TMP86FM25 to External Controller - (Baud rate auto set) OK: Echo back data (5AH) Error: Nothing transmitted - OK: Echo back data Error: A1H x 3, A3H x 3 , 62H x 3 (Note 1) - OK: Echo back data (30H) Error: A1H x 3, A3H x 3 , 63H x 3 (Note 1) - OK: Nothing transmitted Error: Nothing transmitted - OK: Nothing transmitted Error: Nothing transmitted - OK: Nothing transmitted Error: Nothing transmitted - OK: Nothing transmitted Error: Nothing transmitted - OK: Nothing transmitted Error: Nothing transmitted - 5th byte 6th byte Operation command data (30H) - Changed new baud rate Changed new baud rate 7th byte 8th byte 9th byte 10th byte 11th byte 12th byte 13th byte 14th byte 15th byte : m'th byte m'th + 1 byte : n'th - 2 byte n'th - 1 byte n'th byte n'th + 1 byte Address 15H to 08H in which to store Password count (Note 4) Address 07H to 00H in which to store Password count (Note 4) Address 15H to 08H in which to start Password comparison (Note 4) Address 07H to 00H in which to start Password comparison (Note 4) Password string (Note 5) - Intel Hex format (Binary) (Note 2) - - (Wait for the next operation) (Command data) Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate OK: SUM (High) (Note 3) Error: Nothing transmitted OK: SUM (Low) (Note 3) Error: Nothing transmitted - Note 1: "xxH x 3" denotes that operation stops after sending 3 bytes of xxH. For details, refer to 2.1.8 "Error Code". Note 2: Refer to 2.1.10 "Intel Hex Format (Binary)". Note 3: Refer to 2.1.9 "Checksum (SUM)". Note 4: Refer to 2.1.11 "Passwords". Note 5: If all data of addresses from FFE0H to FFFFH are "00H" or "FFH", the passwords comparison is not executed because the device is considered as blank product. However, it is necessary to specify the password count storage addresses and the password comparison start address even though it is a blank product. If a password error occurs, the UART function of TMP86FM25 stops without returning error code to the controller. Therefore, when a password error occurs, the TMP86FM25 should be reset by RESET pin input. 86FM25-32 2004-03-01 Under development TMP86FM25 Description of FLASH memory writing mode 1. The receive data in the 1st byte is the matching data. When the boot program starts in serial PROM mode, TMP86FM25 (Mentioned as "device" hereafter) waits for the matching data (5AH) to receive. Upon receiving the matching data, it automatically adjusts the UART's initial baud rate to 9,600bps. 2. When the device has received the matching data, the device transmits the data "5AH" as an echo back to the controller. If the device can not receive the matching data, the device does not transmit the echo back data and waits for the matching data again with changing baud rate. Therefore, the controller should send the matching data continuously until the device transmits the echo back data. An external controller should transmit a matching data repeatedly till the device transmit an echo back data. The transmission number of times of matching data varies by the frequency of device. For details, refer to Table 2.1.6. The receive data in the 3rd byte is the baud rate modification data. The seven kinds of baud rate modification data shown in Table 2.1.5 are available. Even if baud rate changing is no need, be sure to send the initial baud rate data (28H: 9,600 bps). When the 3rd byte data is one of the baud rate modification data corresponding to the device's operating frequency, the device sends the echo back data which is the same as received baud rate modification data. Then the baud rate is changed. If the 3rd byte data does not correspond to the baud rate modification data, the device stops UART function after sending 3 bytes of baud rate modification error code: (62H). The changing of baud rate is executed after transmitting the echo back data. The receive data in the 5th byte is the command data (30H) to write the FLASH memory. When the 5th byte is one of the operation command data shown in Table 2.1.7, the device sends the echo back data which is the same as received operation command data (in this case, 30H). If the 5th byte data does not correspond to the operation command data, the device stops UART function after sending 3 bytes of operation command error code: (63H). The 7th byte is used as an upper bit (Bit15 to bit8) of the password count storage address. When the receiving is executed correctly (No error), the device does not send any data. If the receiving error or password error occur, the device does not send any data and stops UART function. The 9th byte is used as a lower bit (Bit7 to bit0) of the password count storage address. When the receiving is executed correctly (No error), the device does not send any data. If the receiving error or password error occur, the device does not send any data and stops UART function. The 11th byte is used as an upper bit (Bit15 to bit8) of the password comparison start address. When the receiving is executed correctly (No error), the device does not send any data. If the receiving error or password error occur, the device does not send any data and stops UART function. 3. 4. 5. 6. 7. 8. 9. 10. The 13th byte is used as a lower bit (Bit7 to bit0) of the password comparison start address. When the receiving is executed correctly (No error), the device does not send any data. If the receiving error or password error occur, the device does not send any data and stops UART function. 86FM25-33 2004-03-01 Under development TMP86FM25 11. The 15th through the m'th bytes are the password data. The number of passwords is the data (N) indicated by the password count storage address. The password data are compared for N entries beginning with the password comparison start address. The controller should send N bytes of password data to the device. If the passwords do not match, the device stops UART function without returning error code to the controller. If the data of addresses from FFE0H to FFFFH are all "FFH" or "00H", the comparison of passwords is not executed because the device is considered as a blank product. 12. The receive data in the m'th + 1 through n'th - 2 byte are received as binary data in Intel Hex format. No received data are echoed back to the controller. The data which is not the start mark (3AH for ":") in Intel Hex format is ignored and does not send an error code to the controller until the device receives the start mark. After receiving the start mark, the device receives the data record, that consists of length of data, address, record type, writing data and checksum. After receiving the checksum of data record, the device waits the start mark data (3AH) again. The data of data record is temporarily stored to RAM and then, is written to specified FLASH memory by page (64 bytes) writing. For details of an organization of FLASH, refer to 2.1.7 "FLASH Memory Writing Data Format". Since after receiving an end record, the device starts to calculate the SUM, the controller should wait the SUM after sending the end record. If receive error or Intel Hex format error occurs, the device stops UART function without returning error code to the controller. 13. The n'th - 1 and the n'th bytes are the SUM value that is sent to the controller in order of the upper byte and the lower byte. For details on how to calculate the SUM, refer to 2.1.9 "Checksum (SUM)". The SUM calculation is performed after detecting the end record, but the calculation is not executed when receive error or Intel Hex format error has occurred. The time required to calculate the SUM of the 32 Kbytes of FLASH memory area is approximately 100 ms at fc = 16 MHz. After the SUM calculation, the device sends the SUM data to the controller. After sending the end record, the controller can judge that the transmission has been terminated correctly by receiving the checksum. 14. After sending the SUM, the device waits for the next operation command data. 86FM25-34 2004-03-01 Under development 2.1.6.2 RAM Loader Mode (Operation command: 60H) Table 2.1.9 shows RAM loader mode process. Table 2.1.9 RAM Loader Mode Process Number of Bytes Transferred BOOT ROM 1st byte 2nd byte 3rd byte 4th byte Transfer Data from External CONTROLLER to TMP86FM25 Matching data (5AH) - Baud rate modification data (See Table 2.1.5) - Baud Rate 9600 bps 9600 bps 9600 bps 9600 bps TMP86FM25 Transfer Data from TMP86FM25 to External Controller - (Baud rate auto set) OK: Echo back data (5AH) Error: Nothing transmitted - OK: Echo back data Error: A1H x 3, A3H x 3, 62H x 3 (Note 1) - OK: Echo back data (60H) Error: A1H x 3, A3H x 3, 63H x 3 (Note 1) - OK: Nothing transmitted Error: Nothing transmitted - OK: Nothing transmitted Error: Nothing transmitted - OK: Nothing transmitted Error: Nothing transmitted - OK: Nothing transmitted Error: Nothing transmitted - OK: Nothing transmitted Error: Nothing transmitted - 5th byte 6th byte Operation command data (60H) - Changed new baud rate Changed new baud rate 7th byte 8th byte 9th byte 10th byte 11th byte 12th byte 13th byte 14th byte 15th byte : m'th byte m'th + 1 byte : n'th - 2 byte n'th - 1 byte n'th byte RAM - Address 15H to 08H in which to store Password count (Note 4) Address 07H to 00H in which to store Password count (Note 4) Address 15H to 08H in which to start Password comparison (Note 4) Address 07H to 00H in which to start Password comparison (Note 4) Password string (Note 5) - Intel Hex format (Binary) (Note 2) - - Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate OK: SUM (High) (Note 3) Error: Nothing transmitted OK: SUM (Low) (Note 3) Error: Nothing transmitted The program jumps to the start address of RAM in which the first transferred data has been written. Note 1: "xxH x 3" denotes that operation stops after sending 3 bytes of xxH. For details, refer to 2.1.8 "Error Code". Note 2: Refer to 2.1.10 "Intel Hex Format (Binary)". Note 3: Refer to 2.1.9 "Checksum (SUM)". Note 4: Refer to 2.1.11 "Passwords". Note 5: If all data of addresses from FFE0H to FFFFH are "00H" or "FFH", the passwords comparison is not executed because the device is considered as blank product. However, it is necessary to specify the password count storage addresses and the password comparison start address even though it is a blank product. If a password error occurs, the UART function of TMP86FM25 stops without returning error code to the controller. Therefore, when a password error occurs, the TMP86FM25 should be reset by RESET pin input. 86FM25-35 2004-03-01 Under development TMP86FM25 Note 6: Do not send only end record after transferring of password string. If the TMP86FM25 receives the end record only after reception of password string, it does not operate correctly. Note 7: When the FLASH power supply is turned off in user's program by setting EEPCR 4. 5. 6. 7. 86FM25-36 2004-03-01 Under development 2.1.6.3 FLASH Memory SUM Output Mode (Operation command: 90H) Table 2.1.10 shows FLASH memory SUM output mode process. Table 2.1.10 FLASH Memory SUM Output Process Number of Bytes Transferred BOOT ROM 1st byte 2nd byte 3rd byte 4th byte Transfer Data from External Controller to TMP86FM25 Matching data (5AH) - Baud rate modification data (See Table 2.1.5) - Baud Rate 9600 bps 9600 bps 9600 bps 9600 bps TMP86FM25 Transfer Data from TMP86FM25 to External Controller - (Baud rate auto set) OK: Echo back data (5AH) Error: Nothing transmitted - OK: Echo back data Error: A1H x 3, A3H x 3, 62H x 3 (Note 1) - OK: Echo back data (90H) Error: A1H x 3, A3H x 3, 63H x 3 (Note 1) OK: SUM (High) (Note 2) Error: Nothing transmitted OK: SUM (Low) (Note 2) Error: Nothing transmitted - 5th byte 6th byte Operation command data (90H) - Changed new baud rate Changed new baud rate 7th byte 8th byte 9th byte - - (Wait for the next operation) (Command data) Changed new baud rate Changed new baud rate Changed new baud rate Note 1: "xxH x 3" denotes that operation stops after sending 3 bytes of xxH. For details, refer to 2.1.8 "Error Code". Note 2: Refer to 2.1.9 "Checksum (SUM)" Description of FLASH memory SUM output mode 1. The process of the 1st byte through the 4th byte are the same as FLASH memory writing mode. 2. 3. The receive data in the 5th byte is the FLASH memory SUM command data (90H) to calculate the entire FLASH memory. When the 5th byte is one of the operation command data shown in Table 2.1.7, the device sends the echo back data which is the same as received operation command data (in this case, 90H). If the 5th byte data does not correspond to the operation command data, the device stops UART function after sending 3 bytes of operation command error code: (63H). The 7th and the 8th bytes are the SUM value that is sent to the controller in order of the upper byte and the lower byte. For details on how to calculate the SUM, refer to 2.1.9 "Checksum (SUM)". After sending the SUM, the device waits for the next operation command data. 4. 5. 86FM25-37 2004-03-01 Under development 2.1.6.4 Product Discrimination Code Output Mode (Operation command: C0H) Table 2.1.11 shows product discrimination code output mode process. Table 2.1.11 Product Discrimination Code Output Process Number of Bytes Transferred BOOT ROM 1st byte 2nd byte 3rd byte 4th byte Transfer Data from External Controller to TMP86FM25 Matching data (5AH) - Baud rate modification data (See Table 2.1.5) - Baud Rate 9600 bps 9600 bps 9600 bps 9600 bps TMP86FM25 Transfer Data from TMP86FM25 to External Controller - (Baud rate auto set) OK: Echo back data (5AH) Error: Nothing transmitted - OK: Echo back data Error: A1H x 3, A3H x 3, 62H x 3 (Note 1) - OK: Echo back data (C0H) Error: A1H x 3, A3H x 3, 63H x 3 (Note 1) 3AH 0AH 02H 00H 00H 00H 00H 01H 80H 00H FFH FFH 7FH - Checksum of transferred data (from 9th to 18th byte) End address of ROM Start mark The number of transfer data (from 9th to 18th byte) Length of address (2 bytes) Reserved data Reserved data Reserved data Reserved data The number of ROM block (1 block) First address of ROM 5th byte 6th byte Operation command data (C0H) - Changed new baud rate Changed new baud rate 7th byte 8th byte 9th byte 10th byte 11th byte 12th byte 13th byte 14th byte 15th byte 16th byte 17th byte 18th byte 19th byte 20th byte (Wait for the next operation) (command data) Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Changed new baud rate Note: "xxH x 3" denotes that operation stops after sending 3 bytes of xxH. For details, refer to 2.1.8 "Error Code". Description of product discrimination code output mode 1. The process of the 1st byte through the 4th byte are the same as FLASH memory writing mode. 2. 3. The receive data in the 5th byte is the product discrimination code output command data (C0H). When the 5th byte is one of the operation command data shown in Table 2.1.7, the device sends the echo back data which is the same as received operation command data (in this case, C0H). If the 5th byte data does not correspond to the operation command data, the device stops UART function after sending 3 bytes of operation command error code: (63H). The 7th and the 19th bytes are the product discrimination code. For details, refer to 2.1.12 "Product Discrimination Code". After sending the SUM, the device waits for the next operation command data. 4. 5. 86FM25-38 2004-03-01 Under development 2.1.7 FLASH Memory Writing Data Format TMP86FM25 FLASH area of TMP86FM25 consists of 512 pages and one page size is 64 bytes. Writing to FLASH is executed by page writing. Therefore, it is necessary to send 64 bytes data (for one page) even though only a few bytes data are written. Figure 2.1.5 shows an organization of FLASH area. When the controller sends the writing data to the device, be sure to keep the format described below. 1. The address of data after receiving the FLASH writing command should be the first address of page. For example, in case of page 2, the first address should be 8080H. 2. If the last data's address of data record is not end address of page, the address of the next data record should be the address + 1. For example, if the last data's address is 802FH (Page 0), the address of the next data record should be 8030H (Page 0). Example: :10802000202122232425262728292A2B2C2D2E2FD8 :10803000303132333435363738393A3B3C3D3E3FC8 ' 8020H to 802FH data ' 8030H to 803FH data 3. The last data's address of data record immediately before sending the end record should be the last address of page. For example, in case of page 1, the last data's address of data record should be 807FH. Example: :10807000303132333435363738393A3B3C3D3E3F88 :00000001FF ' 8070H to 807FH data ' End record Note: Do not write only the addresses from FFE0H to FFFFH when all data of FLASH memory are the same data. If these area are only written, the next operation can not be executed because of password error. 1 2 3 4 5 6 7 8 9 A B C D E F Address 8000H 8010H 8020H 8030H 8040H 8050H 8060H 8070H 8080H 8090H 80A0H 80B0H 80C0H : : FF70H FF80H FF90H FFA0H FFB0H FFC0H FFD0H FFE0H FFF0H 0 F Page 0 E F Page 1 E F Page 2 E E F Page 510 E F Page 511 E Note: "F" shows the first address of each page and "E" shows the last address of each page. Figure 2.1.5 Organization of FLASH Area 86FM25-39 2004-03-01 Under development 2.1.8 Error Code TMP86FM25 When the device detects an error, the error codes are sent to the controller. Table 2.1.12 Error Code Transmit Data 62H, 62H, 62H 63H, 63H, 63H A1H, A1H, A1H A3H, A3H, A3H Meaning of Transmit Data Baud rate modification error occurred. Operating command error occurred. Framing error in received data occurred. Overrun error in received data occurred. Note: If password error occurs, the TMP86FM25 doesn't send error codes. 2.1.9 Checksum (SUM) (1) Calculation method SUM consists of byte + byte... + byte, the checksum of which is returned in word as the result. Namely, data is read out in byte and checksum of which is calculated, with the result returned in word. Example: If the data to be calculated consists of the four bytes shown to the left, SUM of the data is A1H + B2H + C3H + D4H = 02EAH SUM (HIGH) = 02H SUM (LOW) = EAH A1H B2H C3H D4H The SUM returned when executing the FLASH memory write command, RAM loader command, or FLASH memory SUM command is calculated in the manner shown above. (2) Calculation data The data from which SUM is calculated are listed in Table 2.1.13 below. Table 2.1.13 Checksum Calculation Data Operating Mode FLASH memory writing mode FLASH memory SUM output mode RAM loader mode Product Discrimination Code Output mode Data written to RAM Checksum of transferred data (from 9th to 18th byte) Calculation Data Data in the entire area (32 Kbytes) of FLASH memory Remarks Even when written to part of the FLASH area, data in the entire memory area (32 Kbytes) is calculated. The length of data, address, record type and checksum in Intel Hex format are not included in SUM. The length of data, address, record type and checksum in Intel Hex format are not included in SUM. For details, refer to 2.1.12 "Product Discrimination Code". 86FM25-40 2004-03-01 Under development 2.1.10 Intel Hex Format (Binary) 1. TMP86FM25 After receiving the checksum of a record, the device waits for the start mark data (3AH for ":") of the next record. Therefore, the device ignores the data, which does not match the start mark data after receiving the checksum of a record. Make sure that once the controller program has finished sending the checksum of the end record, it does not send anything and waits for two bytes of data to be received (Upper and lower bytes of checksum). This is because after receiving the checksum of the end record, the boot program calculates the checksum and returns the calculated checksum in two bytes to the controller. If a receive error or Intel Hex format error occurs, the UART function of TMP86FM25 stops without returning error code to the controller. In the following cases, an Intel Hex format error occurs: * * * * * When the record type is not 00H, 01H, or 02H When a SUM error occurred When the data length of an extended record (Type = 02H) is not 02H When the address of an extended record (Type = 02H) is larger than 1000H and after that, receives the data record When the data length of the end record (Type = 01H) is not 00H 2. 3. 2.1.11 Passwords The eight or more bytes consecutive data in flash memory area can be used as password. In password check, TMP86FM25 compares these data with data which are transmitted from the external controller. The area in which passwords can be specified is located at addresses 8000H to FF9FH. The area from FFA0H to FFFFH can not be specified as passwords area. The device compares the stored passwords with the passwords, which are received from the controller. If all data of addresses from FFE0H to FFFFH are "00H" or "FFH", the passwords comparison is not executed because the device is considered as blank product. It is necessary to specify the password count storage addresses and the password comparison start address even though it is a blank product. Table 2.1.14 shows the password setting in the blank product and non blank product. 86FM25-41 2004-03-01 Under development Table 2.1.14 Password setting in the Blank Product and Non Blank Product Password PNSA (Password count storage addresses) PCSA (Password comparison start address) N (Password count) Setting of password TMP86FM25 Blank Product (Note 1) 8000H PNSA FF9FH 8000H PCSA FF9FH Non Blank Product 8000H PNSA FF9FH 8000H PCSA FFA0 - N 8N Need (Note 2) * No need Note 1: When all data of addresses from FFE0H to FFFFH area are "00H" or "FFH", the device is judged as blank product. Note 2: The same three or more bytes consecutive data can not be used as password. When the password includes the same consecutive data (Three or more bytes), the password error occurs. If the password error occurred, the UART function of device stops without returning error code. Note 3: *: Don't care. Note 4: When the password doesn't match the above condition, the password error occurs. If the password error occurred, the UART function of device stops without returning error code. Note 5: In case of the blank product, the device receives Intel Hex Format immediately after receiving PCSA without receiving password strings. In this time, because the device ignores the data except the start mark data (3AH for ":") as Intel Hex Format data, even if external controller transmitted dummy password strings, process operates correctly. However, if the dummy password strings contain data "3AH", the device detects it as start mark data mistakenly, and device stops process without returning error code. Therefore, if these process becomes issue, the external controller should not transmit the dummy password strings. RXD pin UART 80H 12H 81H 07H 01H 02H 03H 04H 05H 06H 07H 08H PNSA PCSA Password string FLASH memory 8012H 08H "08H" is treated as the number of password. Comparison 8107H 8108H 8109H 810AH Example PNSA = 8012H PCSA = 8107H Password string = 01H, 02H, 03H, 04H, 05H, 06H, 07H, 08H 810BH 810CH 810DH 810EH 01H 02H 03H 04H 05H 06H 07H 08H 8 bytes Figure 2.1.6 Example of password compare 86FM25-42 2004-03-01 Under development 2.1.11.1 Confirmation method of the blank product and non blank product TMP86FM25 The external controller can confirm whether the device is the blank product or not, by transmission of data described below. (1) Executes FLASH memory writing mode or RAM loader mode. (2) Transmits the PNSA and PCSA. (3) Transmits the end record. (4) In case of the blank product, the device sends checksum of flash memory. In case of the non blank product, the device doesn't send checksum of flash memory but the UART function stops without sending any data. The external controller can confirm the blank product and non blank product by receiving checksum. Note: When the UART function stops in non blank product, the TMP86FM25 should be reset by pin reset input for restarting the serial PROM mode. 2.1.11.2 Password String A string of passwords in the received data are compared with the data in the FLASH memory. In the following cases, a password error occurs: * When the received data does not match the data in the FLASH memory 2.1.11.3 Handling of Password Error If a password error occurs, the UART function of TMP86FM25 stops without returning error code to the controller. Therefore, when a password error occurs, the TMP86FM25 should be reset by RESET pin input. 2.1.12 Product Discrimination Code The product discrimination code is a 13-byte data, that includes the start address and the end address of ROM. Table 2.1.15 shows the product discrimination code format. Table 2.1.15 Product Discrimination Code Format Data 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th The Meaning of Data Start mark (3AH) The number of transfer data (from 3rd to 12th byte) Length of address Reserved data Reserved data Reserved data Reserved data The number of ROM block The upper byte of the first address of ROM The lower byte of the first address of ROM The upper byte of the end address of ROM The lower byte of the end address of ROM Checksum of transferred data (from 3rd to 12th byte) In Case of TMP86FM25 3AH 0AH 02H 00H 00H 00H 00H 01H 80H 00H FFH FFH 7FH 86FM25-43 2004-03-01 Under development 2.1.13 Flowchart TMP86FM25 START Setup UART data receive Receive data = "5AH" No Change baud rate (Adjust to 9600 baud source clock) Yes UART data transmit (Transmit data = "5AH") UART data receive UART data transmit (Echoed back the baud rate modification data) Change baud rate by receive data UART data receive Receive data = 30H (FLASH memory writing mode) Receive data = 60H (RAM loader mode) Receive data = 90H (FLASH SUM output mode) Receive data = C0H (Product discrimination code output mode) UART data transmit (Transmit data = 30H) UART data transmit (Transmit data = 60H) UART data transmit (Transmit data = 90H) UART data transmit (Transmit data = C 0H) Password certification (Compare receive data and FLASH data) Password certification (Compare receive data and FLASH data) UART data receive (Intel Hex format) FLASH write process UART data receive (Intel Hex format) RAM write process UART data transmit (Product discrimination code) UART data transmit (Check sum) UART data transmit (Check sum) UART data transmit (Check sum) Jumps to start address of user program 86FM25-44 2004-03-01 Under development Electrical Characteristics Absolute Maximum Ratings Parameter Supply voltage Input voltage Output voltage TMP86FM25 (VSS = 0 V) Pins Rating -0.3 to 4.0 -0.3 to VDD + 0.3 Except V4 pin V4 pin P6 port P1, P2, P34 to P36, P5, P6, P7 ports P30 to P33 port P6 port P1, P2, P34 to P36, P5, P6, P7 ports P30 to P33 port -0.3 to VDD + 0.3 -0.3 to 4.0 -1.8 3.2 30 -30 60 80 350 260 (10 s) -55 to 125 -40 to 85 C mW mA V Symbol VDD VIN VOUT1 VOUT2 IOUT1 IOUT2 IOUT3 IOUT1 Unit Output current (Per 1 pin) Output current (Total) Power dissipation [Topr = 85C] Soldering temperature (Time) Storage temperature Operating temperature IOUT2 IOUT3 PD Tsld Tstg Topr Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. 86FM25-45 2004-03-01 Under development TMP86FM25 Recommended Operating Condition-1 (MCU mode) Parameter Symbol Pins (VSS = 0 V, Topr = -40 to 85C) Condition Min 2.7 Max Unit fc = 16 MHz fc = 4.2 MHz (in case of external clock) Supply voltage VDD fc = 8 MHz (in case of connecting a resonator) fs = 32.768 kHz NORMAL1, 2 mode IDLE0, 1, 2 mode NORMAL1, 2 mode 1.8 IDLE0, 1, 2 mode NORMAL1, 2 mode 1.8 IDLE0, 1, 2 mode SLOW1, 2 mode SLEEP0, 1, 2 mode 1.8 VDD x 0.70 VDD x 0.75 VDD x 0.90 VDD x 0.30 0 VDD x 0.25 VDD x 0.10 1.0 30.0 1.0 30.0 1.650 2.250 3.000 3.000 0.1 4.2 16.0 34.0 8.0 16.0 34.0 1.800 2.700 3.600 VDD 0.47 F V MHz kHz MHz kHz VDD V 3.6 STOP mode VIH1 Input high level VIH2 VIH3 VIL1 Input low level Clock frequency (in case of external clock) Clock frequency (in case of connecting a resonator) LCD reference voltage Capacity for LCD booster circuit VIL2 VIL3 fc fs fc fs V2IN V3IN V4IN V4IN CLCD XIN, XOUT XTIN, XTOUT XIN, XOUT XTIN, XTOUT V2 V3 V4 V4 (Note 3) Except hysteresis input Hysteresis input Except hysteresis input Hysteresis input VDD 2.7 V VDD < 2.7 V VDD 2.7 V VDD < 2.7 V VDD = 1.8 to 3.6 V VDD = 2.7 to 3.6 V VDD = 1.8 to 3.6 V VDD = 1.8 to 3.6 V VDD = 2.7 to 3.6 V VDD = 1.8 to 3.6 V LCDCTL1 Note 1: The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (Supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. Note 2: When LCDCTL1 Supply voltage (VSS = 0 V, Topr = 25C 5C) Min 2.7 Symbol VDD fc Pins Condition 2 MHz fc 16 MHz Max 3.6 Unit V Clock frequency XIN, XOUT VDD = 2.7 to 3.6 V 2.0 16.0 MHz Note: The operating temperature area of serial PROM mode is 25C 5C and the operating area of high frequency of serial PROM mode is different from MCU mode. 86FM25-46 2004-03-01 Under development DC Characteristics Parameter Hysteresis voltage Input current TMP86FM25 (VSS = 0 V, Topr = -40 to 85C) Pins Hysteresis input TEST Sink open drain, Tri-state RESET , STOP Symbol VHS IIN1 IIN2 IIN3 RIN1 RIN2 RFB RFBT ILO VOH VOL IOL Condition VDD = 3.3 V VDD = 3.6 V, VIN = 0 V VDD = 3.6 V, VIN = 3.6 V/0 V VDD = 3.6 V, VIN = 3.6 V VDD = 3.6 V, VIN = 3.6 V VDD = 3.6 V, VIN = 0 V VDD = 3.6 V VDD = 3.6 V VDD = 3.6 V VOUT = 3.4V / 0.2 V VDD = 3.6 V, lOH = -0.6 mA Min - - - - - 100 - - - 3.2 - - - - - - - - - - - - - Typ. 0.4 - - - 70 220 1.2 14 - - - 6 6.0 3.9 3.3 2.5 850 10 850 7 850 6 0.5 Max - -5 5 +5 - 450 - Unit V A Input resistance High-frequency feedback resistor Low-frequency feedback resistor Output leakage current Output high voltage Output low voltage Output low current Supply current in NORMAL1, 2 mode Supply current in IDLE0, 1, 2 mode Supply current in SLOW1 mode Supply current in SLEEP1 mode Supply current in SLEEP0 mode Supply current in STOP mode TEST pull down RESET pull up k XOUT XTOUT Sink open drain, Tri-state C-MOS, Tri-state M - 10 - 0.4 - 7.2 4.8 4.3 3.0 1200 21 1200 17 1200 16 10 A mA V mA A Except XOUT, P30 to P33 VDD = 3.6 V, IOL = 0.9 mA port P30 to P33 ports Fetch area Flash area RAM area VDD = 3.6 V, VOL = 1.0 V VDD = 3.6 V VIN = 3.4V/0.2V fc = 16 MHz fs = 32.768 kHz MNP = "1" MNP = "0" MNPATP = "1" MNPATP = "0" IDD Fetch area Flash area RAM area VDD = 3.6 V VIN = 3.4V/0.2V fs = 32.768 kHz MNP = "1" MNP = "0" MNPATP = "1" MNPATP = "0" MNPATP = "1" MNPATP = "0" VDD = 3.6 V VIN = 3.4 V/0.2 V Note1: Typical values show those at Topr = 25C, VDD = 3.3 V Note2: Input current (IIN1, IIN2): The current through pull-up or pull-down resistor is not included. Note3: IDD does not include IREF current. Note4: The supply currents of SLOW2 and SLEEP2 modes are equivalent to IDLE0, IDLE1, IDLE2. Note5: MNP (MNPWDW) shows bit0 in EEPCR register and ATP(ATPWDW) shows bit1 in EEPCR register. Note6: "Fetch" means reading operation of FLASH data as an instruction by CPU. 86FM25-47 2004-03-01 Under development AD Conversion Characteristics Parameter Analog reference voltage Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Non linearity error Zero point error Full scale error Total error TMP86FM25 (VSS = 0.0 V, 2.7 V VDD 3.6 V, Topr = -40 to 85C) Condition Min VDD - 1.0 2.5 VSS VDD = VAREF = 3.6 V VSS = 0.0 V VDD = 2.7 V VSS = 0.0 V VAREF = 2.7 V - - - - - Symbol VAREF VAREF VAIN IREF Typ. - - - 0.4 - - - - Max VDD - VAREF - 1 1 1 2 Unit V mA LSB (VSS = 0.0 V, 2.0 V VDD < 2.7 V, Topr = -40 to 85C) Parameter Analog reference voltage Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Non linearity error Zero point error Full scale error Total error Symbol VAREF VAREF VAIN IREF Condition Min VDD - 0.6 2.0 VSS Typ. - - - 0.22 - - - - Max VDD - VAREF - 1 1 1 2 Unit V VDD = VAREF = 2.0V VSS = 0.0 V VDD = 2.0 V VSS = 0.0 V VAREF = 2.0 V - - - - - mA LSB (VSS = 0.0 V, 1.8 V VDD < 2.0 V, Topr = -10 to 85C) (Note 5) Parameter Analog reference voltage Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Non linearity error Zero point error Full scale error Total error Symbol VAREF VAREF VAIN IREF Condition Min VDD - 0.1 1.8 VSS Typ. - - - 0.2 - - - - Max VDD - VAREF - 2 2 2 4 Unit V VDD = VAREF = 1.8V VSS = 0.0 V VDD = 1.8 V VSS = 0.0 V VAREF = 1.8 V - - - - - mA LSB Note 1: The total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal conversion line. Note 2: Conversion time is different in recommended value by power supply voltage. Note 3: Please use input voltage to AIN input Pin in limit of VAREF - VSS. When voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel conversion value. Note 4: Analog Reference Voltage Range: VAREF = VAREF - VSS Note 5: When AD is used with VDD < 2.0 V, the guaranteed temperature range varies with the operating voltage. 86FM25-48 2004-03-01 Under development TMP86FM25 AC Characteristics Parameter (VSS = 0 V, VDD = 2.7 to 3.6 V, Topr = -40 to 85C) Symbol Condition NORMAL1, 2 mode IDLE1, 2 mode SLOW1, 2 mode SLEEP1, 2 mode For external clock operation (XIN input) fc = 16 MHz For external clock operation (XTIN input) fs = 32.768 kHz Min 0.25 117.6 - - Typ. - - 31.25 15.26 Max 4 Unit s Machine cycle time tcy 133.3 - - ns s High level clock pulse width Low level clock pulse width High level clock pulse width Low level clock pulse width twcH twcL twcH twcL (VSS = 0 V, VDD = 1.8 to 3.6 V, Topr = -40 to 85C) Parameter Symbol Condition NORMAL1, 2 mode Machine cycle time tcy IDLE1, 2 mode SLOW1, 2 mode SLEEP1, 2 mode High level clock pulse width Low level clock pulse width High level clock pulse width Low level clock pulse width twcH twcL twcH twcL For external clock operation (XIN input) fc = 4.2 MHz For external clock operation (XTIN input) fs = 32.768 kHz Min 0.5 117.6 - - Typ. - - 119.04 15.26 Max 4 Unit s 133.3 - - ns s Timer Counter 1 input (ECIN) Characteristics Parameter TC1 input (ECIN input) (VSS = 0 V, Topr = -40 to 85C) Min - - Symbol tTC1 Condition Frequency measurement mode VDD = 2.7 to 3.6 V Frequency measurement mode VDD = 1.8 to 2.7 V Typ. - - Max 0.5. Unit MHz 0.25 86FM25-49 2004-03-01 Under development UART Timing-1 (VDD = 2.7 V to 3.6 V, fc = 2 MHz to 16 MHz, Ta = 25C) The Number of Clock (fc) Approx. 600 Approx. 700 Approx. 600 Approx. 1573000 TMP86FM25 Parameter Time from the reception of a matching data until the output of an echo back Time from the reception of a Baud Rate Modification Data until the output of an echo back Time from the reception of an operation command until the output of an echo back Calculation time of checksum Symbol CMeb1 CMeb2 CMeb3 CKsm Required Minimum Time At fc = 2 MHz 300 s 350 s 300 s 786.5 ms At fc = 16 MHz 37.5 s 43.7 s 37.5 s 98.3 ms UART Timing-2 (VDD = 2.7 V to 3.6 V, fc = 2 MHz to 16 MHz,Ta = 25C) Parameter Symbol RXsup CMtr1 CMtr2 CMtr3 CMtr4 The Number of Clock (fc) 83850 28500 600 750 950 Required Minimum Time At fc = 2 MHz 41.9 ms 14.3 ms 300 s 375 s 475 s At fc = 16 MHz 5.3 ms 1.8 ms 37.5 s 46.9 s 59.4 s Time from reset release until acceptance of start bit of RXD pin Time between a matching data and the next matching data Time from the echo back of matching data until the acceptance of baud rate modification data Time from the output of echo back of baud rate modification data until the acceptance of an operation command Time from the output of echo back of operation command until the acceptance of Password count storage addresses RXsup RESET pin (TMP86FM25) CMtr2 CMtr3 CMtr4 (5AH) RXD pin (TMP86FM25) (5AH) TXD pin (TMP86FM25) (28H) (28H) (30H) (30H) CMeb1 (5AH) RXD pin (TMP86FM25) TXD pin (TMP86FM25) CMtr1 (5AH) CMeb2 (5AH) CMeb3 Flash Characteristics Parameter (VSS = 0 V) Condition VDD = 2.7 to 3.6 V, 2 MHz fc 16 MHz (Topr = 25C 5C) Min - Typ. - Max 10 5 Unit Times Number of guaranteed writes (Page writing) to Flash memory in serial PROM mode 86FM25-50 2004-03-01 Under development TMP86FM25 Package Dimensions P-QFP100-1420-0.65A Unit: mm 86FM25-51 2004-03-01 Under development TMP86FM25 86FM25-52 2004-03-01 |
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